The blog post examines the implications of quantum computing on public key cryptography and how RISC-V is adapting to implement Post Quantum Cryptography standards.
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FPRox is an enthusiast of computer architecture and arithmetic, with interests in RISC-V.
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This blog post benchmarks the CanMV board with a K230 core, highlighting the use of a new development image from RISE that improves stability and usability compared to the official image. It discusses the setup process, including ...
RIE enables developers to emulate future RISC-V Vector extensions, facilitating application development without immediate hardware support.
RISC-V Vector extensions are evolving with new fast track projects that introduce additional instructions to improve performance in various applications.
The IEEE-754 standard, which specifies binary floating-point arithmetic, recently celebrated its 40th anniversary. The article discusses the history and significance of the standard, its revisions over the years, and key contribut...
The post presents the results of a survey conducted in July 2025 regarding development habits in the RISC-V community. It highlights that Spike is the most popular tool for RISC-V development, used by 38% of respondents, followed ...
The post discusses the author's curiosity about RISC-V development tools and solicits feedback from the community through a poll. The author shares their personal experiences with tools like spike and compilers such as clang and G...
The post reviews the Open Compute Project MX Scaling format standard, its support in hardware, and the ongoing RISC-V extension projects. It discusses the use of small numerical formats in neural networks and the MX scaling format...
The text discusses the RISC-V Vector Reduction Operations, including the element wise pattern and the reduction pattern. It explains the basic pattern for an RVV reduction operation, provides examples of integer and floating-point...
The text discusses the RISC-V Vector 1.0 (RVV) ratified in November 2021, which covers a wide range of ground, with supported element sizes ranging from 8 to 64-bit and offering various formats and operations. It defines a few mor...
The post discusses the optimization of polynomial multiplication using the Number Theoretic Transform algorithm with RISC-V Vector. It details the steps involved in the NTT algorithm and the efforts to optimize the implementation ...
The post discusses implementation techniques to swap pairs of elements using RISC-V Vector. It presents two methods: vslide-based and widening arithmetic, and compares their efficiency. The vslide-based approach is found to be fas...
The text discusses the Number Theoretic Transform (NTT) and its application to polynomial multiplication. It explains the NTT method, its implementation using RISC-V Vector, and the use of Barrett's modular reduction method. It al...
This post describes a way to compute a cycle redundancy check (CRC) hash using RISC-V Vector extension (a.k.a. RVV). It explains the process of CRC, the implementation of CRC in the Linux kernel, and the use of RISC-V Vector Crypt...
The post discusses the CanMV K230 RISC-V board, its features, and the author's initial experience using it. It includes information about the board's hardware, software images, booting a Linux system, building and executing softwa...
The text discusses the RISC-V Scalar Bit Manipulation Extensions, which were ratified in November 2021. It provides detailed information about the Zba, Zbb, Zbc, and Zbs extensions, including the instructions they introduce and th...
The blog post is not an interview, but it requires knowledge of computer architecture, floating-point arithmetic, and deep learning. The effort level to gather the information for this text is rated at 8. The main genre of the tex...
The text discusses the implementation of the Softmax function using RISC-V Vector. It explains the challenges of exponential overflow and presents a method to build an approximation scheme for the exponential. The implementation o...
The text discusses the process of transposing a square matrix using RISC-V Vector. It explains the relation between matrix layouts in memory and computing a matrix transpose, and provides multiple techniques to implement matrix tr...
This post discusses the implementation of the SHA-3 Keccak round function using RISC-V Vector. It includes an introduction to the Keccak algorithm, theoretical study of vectorization, and benchmarking. The post also reviews the ve...
The text discusses RISC-V Vector Programming in C with Intrinsics. It explains how to use RISC-V Vector directly in C/C++ through intrinsics, the types of intrinsics, and the implementation of a basic vector example. It also inclu...
The text discusses the challenges of ensuring forward compatibility of implementations in an ever evolving ISA, and introduces the concept of placeholder encodings in RISC-V, specifically Zimop and Zcmop. These extensions define n...
0RISC-V support for BFloat16
2023-09-04 • machine learning ieee 754 risc-v float16
The text discusses the BFloat16 format, its support in RISC-V, and its applications in machine learning. It explains the IEEE-754 standard, the benefits of BFloat16, and the ongoing efforts to define BFloat16 support in RISC-V. Th...
The text announces the start of a one month public review for a new RISC-V extension called Smcntrpmf. It extends the mode-base filtering functionality of Sscofpmf to some of the base counters. The extension introduces privilege m...