This blog post is the second part of a series on LLVM's Machine Scheduler, focusing on the profitability check phase of instruction scheduling. It explains the importance of register pressure and resource pressure in optimizing in...
About:
Min-Yih "Min" Hsu's Personal Website
Website:
Specializations:
Incoming Links:
Subscribe to RSS:
This blog post provides an in-depth exploration of the Machine Scheduler in LLVM, detailing its design, objectives, and workflow. It explains the evolution from the original DAG scheduler to the current pre-RA and post-RA scheduli...
The text explains how to calculate throughput with LLVM's scheduling model. It describes the scheduling model in LLVM, the basic throughput calculation, and calculating throughput with resource segments. The author also discusses ...
0Visualize RISC-V Vector Memory Instructions
2025-01-05 •
The text discusses the RISC-V Vector (RVV) extension and its load/store instructions, categorizing them into strided and segmented access patterns. It explains the concepts of effective LMUL and SEW, and provides examples of unit-...
0Scheduling Model in LLVM - Part II
2024-10-28 •
The text discusses the scheduling model in LLVM, covering the number of ProcResource units, ProcResGroup, and super resource. It explains how scheduling models are used, how to express hierarchy structure, and the differences betw...
0When LLVM scalable vector meets RISC-V
2024-10-05 •
The text explains how LLVM handles RISC-V Vector Extension (RVV), covering how the RISC-V backend lowers vector types and vector operations. It also discusses the origin of scalable vector types in LLVM and how they map to RISC-V ...
0Scheduling Model in LLVM - Part I
2024-08-05 •
The text discusses the importance of instruction scheduling in modern compilers, focusing on LLVM's scheduling model. It explains how scheduling models are used in LLVM, how to specify scheduling information for individual instruc...
0Legalizations in LLVM Backend
2024-05-15 •
The text discusses the process of legalization in LLVM's code generation pipeline, focusing on SelectionDAG ISel. It explains the steps involved in type legalization and legalizing operations, and how it works in action. It also c...
0Publications
0001-01-01 •
The text is a list of publications and talks by Min-Yih Hsu, covering topics such as LLVM techniques, timing analysis, hybrid throughput analysis, instruction selection, and OpenCL 2.0 compiler adaptation on LLVM for PTX simulator...